CPC G06F 3/064 (2013.01) [G06F 1/3296 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] | 18 Claims |
1. A memory system comprising:
a memory device including a plurality of memory blocks each including a plurality of pages; and
a memory controller configured to:
monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and
execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point,
wherein the memory controller is further configured to set the reference time point as a time point at which the memory system enters an idle state or a low power mode.
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