US 11,954,276 B2
Semiconductor device and touch panel
Shunpei Yamazaki, Tokyo (JP); Hajime Kimura, Tochigi (JP); Masami Jintyou, Tochigi (JP); Yasuharu Hosaka, Tochigi (JP); Naoto Goto, Tochigi (JP); Takahiro Iguchi, Tochigi (JP); Daisuke Kurosaki, Tochigi (JP); and Junichi Koezuka, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on May 11, 2021, as Appl. No. 17/316,768.
Application 17/316,768 is a continuation of application No. 16/830,795, filed on Mar. 26, 2020, granted, now 11,036,324.
Application 16/830,795 is a continuation of application No. 16/452,615, filed on Jun. 26, 2019, abandoned.
Application 16/452,615 is a continuation of application No. 15/091,295, filed on Apr. 5, 2016, granted, now 10,372,274, issued on Aug. 6, 2019.
Claims priority of application No. 2015-081455 (JP), filed on Apr. 13, 2015.
Prior Publication US 2021/0278922 A1, Sep. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/041 (2006.01); G06F 3/044 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10K 59/40 (2023.01)
CPC G06F 3/0412 (2013.01) [G06F 3/0446 (2019.05); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H10K 59/40 (2023.02); G06F 2203/04103 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first substrate;
a second substrate;
a liquid crystal between the first substrate and the second substrate;
a spacer between the first substrate and the second substrate;
a plurality of pixel circuits each comprising a transistor and a pixel electrode, over the first substrate,
a touch sensor comprising a plurality of first electrodes and a plurality of second electrodes, the touch sensor being over the first substrate;
a wiring electrically connected to at least one of the plurality of first electrodes;
the transistor comprising:
a gate electrode;
a gate insulating film;
a semiconductor film having a channel formation region between the gate electrode and the gate insulating film; and
a source electrode and a drain electrode which are electrically connected to the semiconductor film,
a first insulating film over the semiconductor film, the source electrode, and the drain electrode;
a first metal oxide film, a second metal oxide film, and a third metal oxide film which are over and in contact with the first insulating film;
a second insulating film over the first metal oxide film, the second metal oxide film, and the third metal oxide film; and
wherein the pixel electrode is over and in contact with the second insulating film,
wherein the first metal oxide film is configured to function as the first electrode,
wherein the second metal oxide film is configured to function as the second electrode,
wherein the third metal oxide film has a region overlapping with the channel formation region,
wherein the wiring extends in a first direction in a plan view,
wherein the second electrode extends in a second direction intersecting the first direction in the plan view, and
wherein the wiring overlaps with a region between first electrodes adjacent to the second direction among the plurality of first electrodes in the plan view.