US 11,954,206 B2
Systems, methods, and devices for secured nonvolatile memories
Sandeep Krishnegowda, San Jose, CA (US); and Zhi Feng, Fremont, CA (US)
Assigned to Infineon Technologies LLC, San Jose, CA (US)
Filed by Infineon Technologies LLC, San Jose, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,131.
Claims priority of provisional application 63/157,185, filed on Mar. 5, 2021.
Prior Publication US 2022/0284105 A1, Sep. 8, 2022
Int. Cl. G06F 21/57 (2013.01); G06F 3/06 (2006.01); G06F 9/4401 (2018.01); G06F 13/16 (2006.01)
CPC G06F 21/575 (2013.01) [G06F 3/0623 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 9/4403 (2013.01); G06F 13/1668 (2013.01); G06F 2221/034 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
implementing, using a controller of a secured nonvolatile memory, a validation operation on a first portion of code stored in a first secured storage region of the secured nonvolatile memory, the validation operation comprising computing a validation value;
retrieving a second portion of code from a second secured storage region, the second portion of code comprising a pre-computed validation value, the first and second portion of code being associated with booting a processor;
implementing, using the controller, a comparison operation of the validation value and the pre-computed validation value; and
generating, using the controller, a signal based on a result of the comparison operation, the signal being provided to the processor via an interface of the secured nonvolatile memory, and the signal enabling booting of the processor in response to a matching comparison operation performed on the computed validation value and the pre-computed validation value.