CPC G06F 16/2379 (2019.01) [G06F 5/16 (2013.01); G06F 16/245 (2019.01); G06F 16/9027 (2019.01)] | 19 Claims |
1. A computer processing unit for heapifying data elements, comprising:
a memory comprising storage circuitry forming a plurality of register files for storing the data elements, the plurality of register files comprising a parent register file and a first child register file associated with the parent register file;
a plurality of hardware nodes including a parent hardware node and children hardware nodes, each parent hardware node comprising:
first interface circuitry associated with the parent register file and configured for reading a first parent data element from the parent register file and receiving a first child data element and a second child data element from the first child register file; and
first comparison circuitry associated with the parent register file and configured for updating the parent register file and the first child register file, by generating one or more indication signals, based on the first parent data element, the first child data element, and the second child data element according to a given principle;
a multiplexer configured to transceive data elements with other hardware nodes, wherein the first comparison circuitry is configured to receive the first parent data element, the first child data element, and the second child data element from the multiplexer and sequentially perform comparison on two of the first parent data element, the first child data element, and the second child data element.
|