US 11,954,062 B2
Dynamic memory reconfiguration
Joydeep Ray, Folsom, CA (US); Niranjan Cooray, Folsom, CA (US); Subramaniam Maiyuran, Gold River, CA (US); Altug Koker, El Dorado Hills, CA (US); Prasoonkumar Surti, Folsom, CA (US); Varghese George, Folsom, CA (US); Valentin Andrei, San Jose, CA (US); Abhishek Appu, El Dorado Hills, CA (US); Guadalupe Garcia, Chandler, AZ (US); Pattabhiraman K, Bangalore (IN); Sungye Kim, Folsom, CA (US); Sanjay Kumar, Bangalore (IN); Pratik Marolia, Hillsboro, OR (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Vasanth Ranganathan, El Dorado Hills, CA (US); William Sadler, Folsom, CA (US); and Lakshminarayanan Striramassarma, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/310,540
Filed by INTEL CORPORATION, Santa Clara, CA (US)
PCT Filed Mar. 14, 2020, PCT No. PCT/US2020/022838
§ 371(c)(1), (2) Date Aug. 10, 2021,
PCT Pub. No. WO2020/190800, PCT Pub. Date Sep. 24, 2020.
Claims priority of provisional application 62/819,337, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,361, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,435, filed on Mar. 15, 2019.
Prior Publication US 2022/0066931 A1, Mar. 3, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 7/544 (2006.01); G06F 7/575 (2006.01); G06F 7/58 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 12/0866 (2016.01); G06F 12/0871 (2016.01); G06F 12/0875 (2016.01); G06F 12/0882 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/0893 (2016.01); G06F 12/0895 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 12/128 (2016.01); G06F 15/78 (2006.01); G06F 15/80 (2006.01); G06F 17/16 (2006.01); G06F 17/18 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); H03M 7/46 (2006.01); G06N 3/08 (2023.01); G06T 15/06 (2011.01)
CPC G06F 15/7839 (2013.01) [G06F 7/5443 (2013.01); G06F 7/575 (2013.01); G06F 7/588 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30065 (2013.01); G06F 9/30079 (2013.01); G06F 9/3887 (2013.01); G06F 9/5011 (2013.01); G06F 9/5077 (2013.01); G06F 12/0215 (2013.01); G06F 12/0238 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0866 (2013.01); G06F 12/0871 (2013.01); G06F 12/0875 (2013.01); G06F 12/0882 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0893 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 12/128 (2013.01); G06F 15/8046 (2013.01); G06F 17/16 (2013.01); G06F 17/18 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); H03M 7/46 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/3867 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/302 (2013.01); G06F 2212/401 (2013.01); G06F 2212/455 (2013.01); G06F 2212/60 (2013.01); G06N 3/08 (2013.01); G06T 15/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A general-purpose graphics processor comprising:
a cache memory including multiple memory banks;
a cache controller coupled with the cache memory, the cache controller including a dynamic hash unit to select, based on a first hash function and an address associated with a memory access, one or more of the multiple memory banks to store data associated with the memory access; and
cache monitor hardware to monitor an access pattern of the multiple memory banks, the cache monitor hardware further to:
request the dynamic hash unit to select a second hash function for use to select the one or more of the multiple memory banks, the cache monitor hardware to request the selection of the second hash function in response to detection of a bank access pattern disparity over a threshold; and
request the dynamic hash unit to select a third hash function in response to a determination that a temperature of one or more of the multiple memory banks exceeds a threshold, the third hash function different from the second hash function.