US 11,954,047 B2
Circuitry and methods for spatially unique and location independent persistent memory encryption
Mahesh Natu, Folsom, CA (US); Anand K. Enamandram, Folsom, CA (US); Manjula Peddireddy, Santa Clara, CA (US); Robert A. Branch, Portland, OR (US); Tiffany J. Kasanicky, Longmont, CO (US); Siddhartha Chhabra, Portland, OR (US); and Hormuzd Khosravi, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,745.
Prior Publication US 2022/0100679 A1, Mar. 31, 2022
Int. Cl. G06F 12/14 (2006.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01)
CPC G06F 12/1441 (2013.01) [G06F 9/30101 (2013.01); G06F 9/30145 (2013.01); G06F 12/0238 (2013.01); G06F 12/1408 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one persistent range register to indicate a persistent range of memory;
an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and:
append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and
output the address as the output address when the address is not within the persistent range; and
an encryption engine circuit to generate a ciphertext based on the output address.