US 11,954,045 B2
Object and cacheline granularity cryptographic memory integrity
David M. Durham, Beaverton, OR (US); Michael LeMay, Hillsboro, OR (US); Santosh Ghosh, Hillsboro, OR (US); and Sergej Deutsch, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,213.
Prior Publication US 2022/0012188 A1, Jan. 13, 2022
Int. Cl. G06F 12/14 (2006.01); G06F 12/0802 (2016.01); G06F 21/55 (2013.01); G06F 21/56 (2013.01); G06F 21/79 (2013.01)
CPC G06F 12/1408 (2013.01) [G06F 12/0802 (2013.01); G06F 21/554 (2013.01); G06F 2212/466 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A system, comprising:
processor circuitry to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation containing data contents or code contents, wherein the address range includes at least one address in a first cacheline of memory and at least one address in a second cacheline of the memory; and
integrity circuitry to:
identify a first portion of the first cacheline, wherein the first portion of the first cacheline is to include some of the address range and is to be identified based at least in part on a first data bounds value stored in a metadata region located within the first cacheline, wherein the first data bounds value indicates a size of first data of the data contents or first code of the code contents contained within the first portion of the first cacheline;
generate a first integrity value based on the first portion of the first cacheline; and
prevent the memory access operation based on the first integrity value not corresponding to a second integrity value stored in the metadata region.