CPC G06F 12/0815 (2013.01) | 20 Claims |
18. A system, comprising:
a set of processor core complexes;
a cache directory coupled with the set of processor core complexes and configured to store an entry associating a memory region with an exclusive coherency state; and
a controller device coupled with the cache directory and configured to, in response to a memory access directed to the memory region, transmit a demote superprobe to convert at least one cache line associated with the memory region from an exclusive coherency state to a shared coherency state.
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