US 11,954,031 B2
Enhancing cache dirty information
David Symons, Abingdon (GB); and Ezequiel Alves, Abingdon (GB)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 15, 2022, as Appl. No. 17/888,292.
Application 17/888,292 is a continuation of application No. 17/200,149, filed on Mar. 12, 2021, granted, now 11,449,423.
Prior Publication US 2023/0023940 A1, Jan. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0804 (2016.01); G11C 14/00 (2006.01)
CPC G06F 12/0804 (2013.01) [G06F 2212/1032 (2013.01); G11C 14/0018 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A memory storage system external to a host, the memory storage system comprising:
a non-volatile semiconductor memory device configured to store a look-up table (LUT) comprising entries;
a volatile semiconductor memory device configured to temporarily store the entries of the LUT; and
a controller configured to store and retrieve data in the non-volatile semiconductor memory device in response to commands received from the host external to the memory storage system, the controller configured to:
assign a status indicator to each of a plurality of first regions in the LUT and a plurality of second regions in the LUT, the status indicator corresponding to one or more entries of a cached address of the volatile semiconductor memory device belonging to the first region or the second region of the LUT,
update one or more status indicators, each an updated status indicator, and
copy, based on the updated one or more status indicators, the one or more entries in the volatile semiconductor memory device associated with either the first region or the second region containing the updated status indicator to the non-volatile semiconductor memory device.