US 11,954,026 B1
Paging hierarchies for extended page tables and extended page attributes
David Kaplan, Austin, TX (US); and David S. Christie, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Sep. 17, 2019, as Appl. No. 16/572,833.
Claims priority of provisional application 62/732,925, filed on Sep. 18, 2018.
Int. Cl. G06F 12/00 (2006.01); G06F 9/455 (2018.01); G06F 12/06 (2006.01); G06F 12/1009 (2016.01); G06F 13/00 (2006.01)
CPC G06F 12/0615 (2013.01) [G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/151 (2013.01); G06F 2212/152 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A processing system, comprising:
a processor core; and
a memory management unit (MMU) configured to:
store a page table set in a memory accessible by the processing system, wherein:
at least a first page table of the page table set is configured as a non-extended page table and a last page table of the page table set is configured as an extended page table, and
the extended page table includes an extended page table entry having extended page table attributes associated with a physical memory page;
receive a request to translate a virtual address into a physical address associated with the physical memory page; and
using a same set of bits of the virtual address, access a pointer to the extended page table entry in a non-extended page table of the page table set and retrieve an extended page attribute of the physical memory page from the extended page table entry based on the pointer.