US 11,954,025 B2
Systems and methods for reading and writing sparse data in a neural network accelerator
Ganesh Venkatesh, San Jose, CA (US); Liangzhen Lai, Fremont, CA (US); Pierce I-Jen Chuang, Sunnyvale, CA (US); and Meng Li, Newark, CA (US)
Assigned to Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed by Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed on Mar. 24, 2023, as Appl. No. 18/126,228.
Application 18/126,228 is a continuation of application No. 16/509,138, filed on Jul. 11, 2019, granted, now 11,630,770.
Prior Publication US 2023/0229591 A1, Jul. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/04 (2006.01); G06N 3/08 (2023.01)
CPC G06F 12/04 (2013.01) [G06F 2212/1028 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
accessing, by circuitry, a mask identifying byte positions within a data word having non-zero values in memory, wherein each bit of the mask has a first value or a second value, the first value indicating that a byte of the data word corresponds to a non-zero byte value, the second value indicating that the byte of the data word corresponds to a zero byte value;
modifying, by the circuitry, the data word to have non-zero byte values stored at an end of a first side of the data word in the memory, and any zero byte values stored in a remainder of the data word; and
writing, by the circuitry, the modified data word to the memory via at least a first slice of a plurality of slices that is configured to access the first side of the data word in the memory.