CPC G06F 11/079 (2013.01) [G06F 11/073 (2013.01); G06F 11/0772 (2013.01); G06F 13/00 (2013.01); G11C 5/04 (2013.01); G11C 7/20 (2013.01); G11C 8/12 (2013.01); G11C 29/26 (2013.01); G11C 29/44 (2013.01)] | 20 Claims |
1. A memory controller to control the operation of a dynamic random access memory (DRAM) device having a plurality of memory cells, the memory controller comprising:
a control interface to transmit to the DRAM device:
a memory access command that specifies an access to the plurality of memory cells; and,
a first register access command that specifies a first register access;
a data interface to transmit to the DRAM device:
in connection with the memory access command, data to be stored in the plurality of memory cells; and
in connection with the first register access command, a code to indicate to the DRAM device that the DRAM device is to store a device identification value.
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