US 11,953,980 B2
Memory sub-system with dynamic calibration using component-based function(s)
Gerald L. Cadloni, Longmont, CO (US); Bruce A. Liikanen, Berthoud, CO (US); and Violante Moschiano, Avezzano (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 1, 2022, as Appl. No. 18/073,402.
Application 18/073,402 is a continuation of application No. 17/200,893, filed on Mar. 14, 2021, granted, now 11,526,393.
Application 17/200,893 is a continuation of application No. 16/013,031, filed on Jun. 20, 2018, granted, now 10,990,466, issued on Apr. 27, 2021.
Prior Publication US 2023/0099349 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G06F 11/079 (2013.01) [G06F 11/073 (2013.01); G06F 11/0751 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a circuit configured to generate, in response to a data access command from a controller during read level voltage calibration, two or more read results based on reading a set of memory cells using a read level voltage along with at least one offset read voltage, wherein --
the two or more read results are generated as samples used in calibrating the read level voltage initially configured for use in response to a read command.