US 11,953,971 B2
Method for extending hold-up time
Manuel Escudero Rodriguez, Villach (AT); David Meneses Herrera, Helsinki (FI); and Matteo-Alessandro Kutschak, Ludmannsdorf (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jun. 8, 2022, as Appl. No. 17/835,520.
Claims priority of application No. 21180669 (EP), filed on Jun. 21, 2021.
Prior Publication US 2022/0404896 A1, Dec. 22, 2022
Int. Cl. G06F 1/3296 (2019.01); G06F 1/3287 (2019.01); H02J 7/34 (2006.01)
CPC G06F 1/3296 (2013.01) [G06F 1/3287 (2013.01); H02J 7/345 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method, comprising:
operating a buffer circuit in a first operating mode or a second operating mode,
wherein operating the buffer circuit in the first operating mode comprises buffering, by a first capacitor of the buffer circuit, power provided by a power source and received by a load,
wherein operating the buffer circuit in the second operating mode comprises:
connecting a second capacitor in series with the first capacitor to form a capacitor series circuit;
supplying power to the load by the capacitor series circuit; and
regulating a first voltage across the capacitor series circuit,
wherein regulating the first voltage comprises transferring charge from the first capacitor to the second capacitor,
wherein the method further comprises:
monitoring an input voltage received by the power source; and
operating the buffer circuit in the second operating mode when the input voltage is zero for longer than a predefined time period.