US 11,953,774 B2
Display substrate, liquid crystal display panel, and liquid crystal display device
Xinlan Yang, Beijing (CN); Wenkai Mu, Beijing (CN); Yi Liu, Beijing (CN); Jun Fan, Beijing (CN); Bo Feng, Beijing (CN); Yang Wang, Beijing (CN); Zhan Wei, Beijing (CN); Tengfei Ding, Beijing (CN); Shijun Wang, Beijing (CN); and Chengfu Xu, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/921,085
Filed by Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jun. 8, 2021, PCT No. PCT/CN2021/098815
§ 371(c)(1), (2) Date Oct. 24, 2022,
PCT Pub. No. WO2022/022070, PCT Pub. Date Feb. 3, 2022.
Claims priority of application No. 202010742149.2 (CN), filed on Jul. 29, 2020.
Prior Publication US 2023/0168534 A1, Jun. 1, 2023
Int. Cl. G02F 1/1335 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G06V 40/13 (2022.01); H01L 27/12 (2006.01)
CPC G02F 1/133512 (2013.01) [G02F 1/13338 (2013.01); G02F 1/134345 (2021.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G06V 40/1318 (2022.01); H01L 27/124 (2013.01); G02F 1/13439 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A display substrate, comprising
a base substrate;
a plurality of sub-pixels on the base substrate, every two rows of sub-pixels constituting a pixel group;
a plurality of first gate lines at first row gaps between adjacent pixel groups, two first gate lines being arranged at each first row gap; and
a plurality of photosensors; wherein orthographic projections of each row of photosensors on the base substrate completely cover a second row gap in the pixel group, and partially overlap with orthographic projections of the sub-pixels;
wherein each of the sub-pixels comprises:
a first transistor between a layer where the plurality of photosensors are located and the base substrate; and
a planar common electrode, an insulating layer and a slit pixel electrode sequentially located on a side, facing away from a layer where the first transistors are located, of the layer where the plurality of photosensors are located;
wherein in one first row gap, one row of the first transistors is electrically connected to one first gate line at the first row gap, and another row of the first transistors is electrically connected to another first gate line at the first row gap; and
the slit pixel electrodes are electrically connected to the first transistors.