US 11,953,766 B2
Parity time symmetric directional couplers with phase tuning
Stanley Cheung, Milpitas, CA (US); Geza Kurczveil, Santa Barbara, CA (US); Yuan Yuan, Milpitas, CA (US); Xian Xiao, Santa Barbara, CA (US); and Raymond G. Beausoleil, Milpitas, CA (US)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP, Houston, TX (US)
Filed on Jun. 17, 2022, as Appl. No. 17/843,352.
Prior Publication US 2023/0408852 A1, Dec. 21, 2023
Int. Cl. G02F 1/017 (2006.01)
CPC G02F 1/01708 (2013.01) 20 Claims
OG exemplary drawing
 
1. A hybrid III-V/silicon device comprising:
a first silicon layer disposed over a buried oxide (BOX) layer, wherein the first silicon layer includes:
a first doped region having a first trench,
a second doped region having a second trench,
a first gap region disposed between the first doped region and the second doped region;
a first oxide layer disposed over the first doped region and the second doped region;
a first mesa disposed on the first doped region of the first silicon layer, wherein the first mesa includes:
a first Group III-V layer disposed over the first oxide layer;
a first optically active region disposed over the first Group III-V layer; and
a second Group III-V layer disposed over the optically active region; and
a second mesa disposed on the second doped region of the first silicon layer, wherein the second mesa includes:
a third Group III-V layer disposed over the first oxide layer;
a second optically active region disposed over the third Group III-V layer; and
a fourth Group III-V layer disposed over the second optically active region.