CPC G01N 27/225 (2013.01) [H01L 23/3171 (2013.01); H01L 23/642 (2013.01)] | 20 Claims |
9. An integrated circuit, comprising:
a silicon substrate;
circuitry on or over said silicon substrate, the circuitry including top-level metal interconnects;
a primary passivation barrier over said top-level metal interconnects;
conductive vias through said primary passivation barrier to said top-level metal interconnects;
a capacitor above said primary passivation barrier and electrically coupled through said conductive vias to said circuitry, said capacitor comprising interdigitated metal fingers with spaces therebetween;
a secondary passivation barrier over said capacitor; and,
a hygroscopic material layer over said secondary passivation barrier, wherein said capacitor is operable to exhibit a capacitance value responsive to moisture present in said hygroscopic material layer and said circuitry is operable to generate a signal responsive to said capacitance value.
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