US RE50,373 E1
Reading from a mode register having different read and write timing
Christopher E. Cox, Placerville, CA (US); and Bill Nale, Livermore, CA (US)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Aug. 25, 2021, as Appl. No. 17/411,627.
Application 17/411,627 is a reissue of application No. 15/721,052, filed on Sep. 29, 2017, granted, now 10,395,722, issued on Aug. 27, 2019.
Int. Cl. G11C 8/18 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/06 (2006.01); G11C 11/4076 (2006.01); G11C 11/409 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 12/0623 (2013.01); G06F 12/0646 (2013.01); G06F 13/1673 (2013.01); G11C 7/1045 (2013.01); G11C 7/1051 (2013.01); G11C 7/1072 (2013.01); G11C 7/227 (2013.01); G11C 8/06 (2013.01); G11C 11/409 (2013.01)] 26 Claims
OG exemplary drawing
 
[ 26. A memory device, comprising:
a decision feedback equalization (DFE) mode register to store configuration information to control operation of the memory device, wherein a write of the configuration information to the DFE mode register by a host takes less time than a read of the configuration information from the DFE mode register by the host; and
a mailbox register separate from the DFE mode register to provide data for a read of the configuration information by the host, wherein the DFE mode register shares the configuration information with the mailbox register to enable the host to read the configuration information from the mailbox register,
wherein the DFE mode register is write-only with respect to the host.]