US RE50,370 E1
Active-by-active programmable device
Alireza Kaviani, San Jose, CA (US); Pongstorn Maidee, San Jose, CA (US); and Ivo Bolsens, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Aug. 24, 2022, as Appl. No. 17/880,487.
Application 17/880,487 is a continuation of application No. 16/891,972, filed on Jun. 18, 2020, granted, now RE49163.
Application 16/891,972 is a reissue of application No. 15/013,696, filed on Feb. 2, 2016, granted, now 10,002,100, issued on Jun. 19, 2018.
Application 17/880,487 is a reissue of application No. 15/013,696, filed on Feb. 2, 2016, granted, now 10,002,100, issued on Jun. 19, 2018.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/36 (2006.01); G06F 13/00 (2006.01); G06F 13/362 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/4031 (2013.01) [G06F 13/362 (2013.01); G06F 13/4068 (2013.01)] 22 Claims
OG exemplary drawing
 
[ 20. An integrated circuit (IC) system, comprising:
a package substrate having a first integrated circuit (IC) die and a companion IC die mounted thereon, the first IC die including a fabric and the companion IC die including application input/output (IO) circuitry, wherein the first IC die does not include application IO circuitry;
a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the first IC die, a second SiP IO circuit disposed in the companion IC die, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit;
first aggregation and first dispersal circuits in the first IC die coupled between the fabric and the first SiP IO circuit; and
second aggregation and second dispersal circuits in the companion IC die coupled between the application IO circuitry and the second SiP IO circuit;
wherein the first and second SiP IO circuits are configured to multiplex multi-channel output of the first and second aggregation circuits, respectively, onto a plurality of physical channels implemented over the conductive interconnect; and de-multiplex input from the plurality of physical channels implemented over the conductive interconnect onto multi-channel input of the first and second dispersal circuits, respectively.]