US 12,274,183 B2
Memory cell with top electrode via
Ming-Che Ku, Hsinchu (TW); Harry-Hak-Lay Chuang, Zhubei (TW); Hung Cho Wang, Taipei (TW); Tsun Chung Tu, Tainan (TW); Jiunyu Tsai, Hsinchu (TW); and Sheng-Huang Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 16, 2023, as Appl. No. 18/511,133.
Application 17/009,905 is a division of application No. 16/416,555, filed on May 20, 2019, granted, now 10,790,439, issued on Sep. 29, 2020.
Application 18/511,133 is a continuation of application No. 17/872,520, filed on Jul. 25, 2022, granted, now 11,889,769.
Application 17/872,520 is a continuation of application No. 17/009,905, filed on Sep. 2, 2020, granted, now 11,489,107, issued on Nov. 1, 2022.
Claims priority of provisional application 62/702,581, filed on Jul. 24, 2018.
Prior Publication US 2024/0090340 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 50/80 (2023.01); G11C 11/16 (2006.01); H01F 10/32 (2006.01); H01F 41/34 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01)
CPC H10N 50/80 (2023.02) [H01F 10/3254 (2013.01); H01F 41/34 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); G11C 11/161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a memory device surrounded by a dielectric structure disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode;
a bottom electrode via coupling the bottom electrode to a lower interconnect; and
a top electrode via coupling the top electrode to an upper interconnect, wherein a bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.
 
6. An integrated chip, comprising:
a substrate;
a conductive structure arranged over the substrate; and
an upper interconnect structure on the conductive structure, wherein a bottom surface of the upper interconnect structure is laterally off-centered from a top of the upper interconnect structure by a non-zero distance.
 
14. An integrated chip, comprising:
an interconnect via disposed within a dielectric structure over a substrate and coupled to an interconnect wire;
wherein a first imaginary line is tangent to a first outermost sidewall of the interconnect via and a second imaginary line is tangent to an opposing second outermost sidewall of the interconnect via, as viewed in a cross-sectional view; and
wherein the first imaginary line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second imaginary line is oriented at a second angle with respect to the horizontal plane, the second angle being less than the first angle.