US 12,274,182 B2
Sidewall spacer structure for memory cell
Yao-Wen Chang, Taipei (TW); Chung-Chiang Min, Zhubei (TW); Harry-Hak-Lay Chuang, Zhubei (TW); Hung Cho Wang, Taipei (TW); Tsung-Hsueh Yang, Taichung (TW); Yuan-Tai Tseng, Zhubei (TW); Sheng-Huang Huang, Hsinchu (TW); and Chia-Hua Lin, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 3, 2023, as Appl. No. 18/364,697.
Application 17/406,355 is a division of application No. 16/601,723, filed on Oct. 15, 2019, granted, now 11,121,308, issued on Sep. 14, 2021.
Application 18/364,697 is a continuation of application No. 17/406,355, filed on Aug. 19, 2021, granted, now 11,818,962.
Prior Publication US 2023/0389445 A1, Nov. 30, 2023
Int. Cl. H10N 50/80 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC H10N 50/80 (2023.02) [H10B 61/22 (2023.02); H10N 50/01 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a dielectric structure overlying a substrate;
a memory cell disposed within the dielectric structure, wherein the memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode;
an upper conductive structure disposed in the dielectric structure and on the top electrode, wherein the upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode; and
a sidewall spacer structure disposed around the memory cell, wherein the sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer, wherein the protrusion contacts the second sidewall spacer layer, wherein a lateral segment of the second sidewall spacer layer extends along and directly contacts an upper lateral surface of the first sidewall spacer layer.