| CPC H10N 50/01 (2023.02) [H10B 61/22 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
|
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, the substrate comprising a logic region and a memory region;
depositing a bottom electrode layer across the logic region and the memory region;
depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
depositing a sacrificial layer over the MTJ layer;
etching and removing the sacrificial layer in the memory region to expose the MTJ layer in the memory region, while keeping the MTJ layer in the logic region covered;
depositing a first conductive layer in the memory region and the logic region after etching the sacrificial layer such that the first conductive layer is in contact with the MTJ layer in the memory region and the sacrificial layer separates the MTJ layer from the first conductive layer in the logic region;
patterning the first conductive layer to expose the MTJ layer in the memory region; and
patterning the MTJ layer and the bottom electrode layer using the patterned first conductive layer as an etching mask to form a MTJ cell structure in the memory region.
|