US 12,274,136 B2
Organic light emitting diode display substrate and preparing method thereof, and organic light emitting diode display apparatus
Hongjun Zhou, Beijing (CN); and Lili Du, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/425,949
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Oct. 22, 2020, PCT No. PCT/CN2020/122895
§ 371(c)(1), (2) Date Jul. 27, 2021,
PCT Pub. No. WO2022/082631, PCT Pub. Date Apr. 28, 2022.
Prior Publication US 2022/0320241 A1, Oct. 6, 2022
Int. Cl. H10K 59/131 (2023.01); G01R 31/28 (2006.01); H01L 23/00 (2006.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01)
CPC H10K 59/131 (2023.02) [G01R 31/2884 (2013.01); H10K 71/00 (2023.02); H01L 24/06 (2013.01); H01L 2224/06155 (2013.01); H10K 59/1201 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a display region, and a peripheral region surrounding the display region, wherein the peripheral region comprises a circuit board pin region and a test pin region located on at least one side of the display region; and the display substrate comprises:
a plurality of sub-pixels located in the display region;
a first power supply line, located in the display region, and electrically connected with the plurality of sub-pixels;
at least one first bonding power supply pin, located in the circuit board pin region, electrically connected with the first power supply line, and configured to transmit a first power supply signal to the plurality of sub-pixels in a display stage;
a second power supply line, located in the peripheral region and surrounding the display region;
at least one second bonding power supply pin, located in the circuit board pin region, electrically connected with the second power supply line, and configured to transmit a second power supply signal to the plurality of sub-pixels in the display stage; and
at least one test power supply pin, located in the test pin region, and electrically connected to at least one of the first power supply line and the second power supply line, the at least one test power supply pin being configured to transmit at least one of the first power supply signal and the second power supply signal to the plurality of sub-pixels in a test stage,
wherein the at least one test power supply pin comprises a first test power supply pin and a second test power supply pin, wherein the first test power supply pin is electrically connected with the first power supply line, and the second test power supply pin is electrically connected with the second power supply line,
wherein the display substrate further comprises a first connecting line, a second connecting line, a first test power lead and a second test power lead, wherein the first test power lead extends along a first direction, the second test power lead extends along the first direction, the first connecting line extends along a second direction, the second connecting line extends along the second direction, and the first direction intersects with the second direction,
wherein the first test power lead is electrically connected with the first connecting line and the first test power supply pin, and the second test power lead is electrically connected with the second connecting line and the second test power supply pin,
wherein the first test power supply pin and the second test power supply pin are disposed independently and do not share the at least one first bonding power supply pin and the at least one second bonding power supply pin in the circuit board pin region,
wherein the first test power supply pin comprises a first sub-layer and a second sub-layer, wherein the first sub-layer is electrically connected with the second sub-layer, the first sub-layer is disposed on a same layer as a first gate metal layer, and the second sub-layer is disposed on a same layer as a first source-drain metal layer,
wherein the second test power supply pin comprises a third sub-layer and a fourth sub-layer, wherein the third sub-layer and the fourth sub-layer are electrically connected, the third sub-layer is disposed on a same layer as the first gate metal layer, and the fourth sub-layer is disposed on a same layer as the first source-drain metal layer,
wherein the first bonding power supply pin comprises a seventh sub-layer and an eighth sub-layer, wherein the seventh sub-layer and the eighth sub-layer are electrically connected, the seventh sub-layer is disposed on a same layer as the first gate metal layer, and the eighth sub-layer is disposed on a same layer as the first source-drain metal layer, and
wherein the second bonding power supply pin comprises a fifth sub-layer and a sixth sub-layer, wherein the fifth sub-layer may be electrically connected with the sixth sub-layer, the fifth sub-layer is disposed on a same layer as the first gate metal layer, and the sixth sub-layer is disposed on a same layer as the first source-drain metal layer.
 
14. A method for preparing a display substrate, the display substrate comprising a display region and a peripheral region surrounding the display region, wherein the peripheral region comprises a circuit board pin region and a test pin region located on one side of the display region, the display region comprises a first power supply line and a plurality of sub-pixels, the peripheral region comprises a second power supply line, the circuit board pin region comprises at least one first bonding power supply pin and at least one second bonding power supply pin, and the test pin region comprises at least one test power supply pin, the method comprising:
sequentially forming a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, and a second gate metal layer on a substrate;
forming a fourth insulating layer on the second gate metal layer; and
forming a first source-drain metal layer, the first power supply line, the second power supply line, the at least one first bonding power supply pin, the at least one second bonding power supply pin, and at least one of the test power supply pin on the fourth insulating layer; the first power supply line is electrically connected with the at least one first bonding power supply pin, the second power supply line is electrically connected with the at least one second bonding power supply pin, and the at least one test power supply pin is electrically connected with at least one of the first power supply line and the second power supply line,
wherein the at least one test power supply pin comprises a first test power supply pin and a second test power supply pin, wherein the first test power supply pin is electrically connected with the first power supply line, and the second test power supply pin is electrically connected with the second power supply line,
wherein the display substrate further comprises a first connecting line, a second connecting line, a first test power lead and a second test power lead, wherein the first test power lead extends along a first direction, the second test power lead extends along the first direction, the first connecting line extends along a second direction, the second connecting line extends along the second direction, and the first direction intersects with the second direction,
wherein the first test power lead is electrically connected with the first connecting line and the first test power supply pin, and the second test power lead is electrically connected with the second connecting line and the second test power supply pin,
wherein the first test power supply pin and the second test power supply pin are disposed independently and do not share the at least one first bonding power supply pin and the at least one second bonding power supply pin in the circuit board pin region,
wherein the first test power supply pin comprises a first sub-layer and a second sub-layer, wherein the first sub-layer is electrically connected with the second sub-layer, the first sub-layer is disposed on a same layer as the first gate metal layer, and the second sub-layer is disposed on a same layer as the first source-drain metal layer,
wherein the second test power supply pin comprises a third sub-layer and a fourth sub-layer, wherein the third sub-layer and the fourth sub-layer are electrically connected, the third sub-layer is disposed on a same layer as the first gate metal layer, and the fourth sub-layer is disposed on a same layer as the first source-drain metal layer,
wherein the first bonding power supply pin comprises a seventh sub-layer and an eighth sub-layer, wherein the seventh sub-layer and the eighth sub-layer are electrically connected, the seventh sub-layer is disposed on a same layer as the first gate metal layer, and the eighth sub-layer is disposed on a same layer as the first source-drain metal layer, and
wherein the second bonding power supply pin comprises a fifth sub-layer and a sixth sub-layer, wherein the fifth sub-layer may be electrically connected with the sixth sub-layer, the fifth sub-layer is disposed on a same layer as the first gate metal layer, and the sixth sub-layer is disposed on a same layer as the first source-drain metal layer.