US 12,274,095 B2
Semiconductor device and electronic device
Hajime Kimura, Atsugi (JP); Atsushi Umezaki, Isehara (JP); and Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Apr. 2, 2024, as Appl. No. 18/624,525.
Application 18/624,525 is a continuation of application No. 17/101,188, filed on Nov. 23, 2020, granted, now 11,961,843.
Application 17/101,188 is a continuation of application No. 16/823,785, filed on Mar. 19, 2020, granted, now 10,854,641, issued on Dec. 1, 2020.
Application 16/823,785 is a continuation of application No. 16/426,461, filed on May 30, 2019, granted, now 10,600,818, issued on Mar. 24, 2020.
Application 16/426,461 is a continuation of application No. 16/004,882, filed on Jun. 11, 2018, granted, now 10,312,267, issued on Jun. 4, 2019.
Application 16/004,882 is a continuation of application No. 15/665,701, filed on Aug. 1, 2017, granted, now 10,002,888, issued on Jun. 19, 2018.
Application 15/665,701 is a continuation of application No. 15/159,131, filed on May 19, 2016, granted, now 9,735,180, issued on Aug. 15, 2017.
Application 15/159,131 is a continuation of application No. 14/887,517, filed on Oct. 20, 2015, granted, now 9,349,757, issued on May 24, 2016.
Application 14/887,517 is a continuation of application No. 14/508,083, filed on Oct. 7, 2014, granted, now 9,171,868, issued on Oct. 27, 2015.
Application 14/508,083 is a continuation of application No. 13/763,804, filed on Feb. 11, 2013, granted, now 8,890,146, issued on Nov. 18, 2014.
Application 13/763,804 is a continuation of application No. 12/960,659, filed on Dec. 6, 2010, granted, now 8,415,665, issued on Apr. 9, 2013.
Claims priority of application No. 2009-282268 (JP), filed on Dec. 11, 2009.
Prior Publication US 2024/0258334 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1334 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/40 (2025.01); H10D 62/80 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 86/60 (2025.01) [G02F 1/133345 (2013.01); G02F 1/1334 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 3/2007 (2013.01); G09G 3/36 (2013.01); H10D 30/67 (2025.01); H10D 30/6704 (2025.01); H10D 30/6756 (2025.01); H10D 30/6757 (2025.01); H10D 62/402 (2025.01); H10D 62/80 (2025.01); H10D 86/0221 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); G02F 1/133302 (2021.01); G02F 1/13345 (2021.01); G09G 2300/0426 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0252 (2013.01); G09G 2320/0257 (2013.01); G09G 2330/021 (2013.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor;
a second transistor,
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor; and
an eighth transistor,
wherein the first to the eighth transistors have the same polarity,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the third transistor is electrically connected to the fourth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the third wiring,
wherein a gate of the sixth transistor is electrically connected to a gate of the fifth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the third wiring,
wherein a gate of the eighth transistor is electrically connected to a gate of the seventh transistor,
wherein the gate of the second transistor and the gate of the fourth transistor are electrically connected to a fifth wiring,
wherein the gate of the fifth transistor and the gate of the sixth transistor are electrically connected to a sixth wiring,
wherein the gate of the seventh transistor and the gate of the eighth transistor are electrically connected to a seventh wiring,
wherein a channel width of the second transistor is larger than a channel width of the fourth transistor,
wherein a channel width of the fifth transistor is larger than a channel width of the sixth transistor, and
wherein a channel width of the seventh transistor is larger than a channel width of the eighth transistor.