US 12,274,094 B2
Gate driving circuit and manufacturing method therefor, array substrate, and display device
Tongshang Su, Beijing (CN); Jun Cheng, Beijing (CN); Bin Zhou, Beijing (CN); Ce Zhao, Beijing (CN); Qinghe Wang, Beijing (CN); Jun Wang, Beijing (CN); and Liangchen Yan, Beijing (CN)
Assigned to Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/801,003
Filed by Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Oct. 12, 2021, PCT No. PCT/CN2021/123296
§ 371(c)(1), (2) Date Aug. 19, 2022,
PCT Pub. No. WO2022/111086, PCT Pub. Date Jun. 2, 2022.
Claims priority of application No. 202011356542.4 (CN), filed on Nov. 27, 2020.
Prior Publication US 2023/0086999 A1, Mar. 23, 2023
Int. Cl. H01L 27/12 (2006.01); G09G 3/20 (2006.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H10D 86/60 (2025.01) [G09G 3/20 (2013.01); H10D 86/0221 (2025.01); H10D 86/441 (2025.01); G09G 2300/0408 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2330/021 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A gate driving circuit, comprising: a plurality of first transistors; wherein at least one first target transistor of the plurality of first transistors comprises:
a first light-shielding layer disposed on a side of a base substrate, the first light-shielding layer being made of a conductive material;
a first gate metal layer and a first source/drain metal layer disposed on a side of the first light-shielding layer away from the base substrate, wherein the first light-shielding layer is connected to the first gate metal layer;
an active layer and a gate insulating layer, wherein the active layer, the gate insulating layer, the first gate metal layer, and the first source/drain metal layer are sequentially laminated along a direction away from the first light-shielding layer; and
a buffer layer, an interlayer dielectric layer, and a passivation layer; wherein the buffer layer is disposed between the first light-shielding layer and the active layer; the interlayer dielectric layer is disposed between the first source/drain metal layer and the first gate metal layer; and the passivation layer is disposed on a side of the first source/drain metal layer away from the interlayer dielectric layer;
wherein the passivation layer, the buffer layer, and the interlayer dielectric layer are provided with a first via hole therein; the passivation layer and the interlayer dielectric layer are further provided with a second via hole therein; and the at least one first target transistor further comprises: a first connection portion; wherein the first connection portion is connected to the first light-shielding layer through the first via hole, and is connected to the first gate metal layer through the second via hole.