US 12,274,092 B2
Resistance measuring structures of stacked devices
Byounghak Hong, Albany, NY (US); Seunghyun Song, Albany, NY (US); Myunggil Kang, Hwaseong-si (KR); and Kang-Ill Seo, Albany, NY (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 8, 2024, as Appl. No. 18/406,345.
Application 18/406,345 is a continuation of application No. 17/382,149, filed on Jul. 21, 2021, granted, now 11,901,363.
Claims priority of provisional application 63/188,508, filed on May 14, 2021.
Prior Publication US 2024/0145479 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 86/00 (2025.01); G01R 27/02 (2006.01); H01L 21/66 (2006.01); H01L 23/535 (2006.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01)
CPC H10D 86/201 (2025.01) [G01R 27/02 (2013.01); H01L 23/535 (2013.01); H10D 86/215 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A resistance measuring structure comprising:
a first Complementary Field Effect Transistor (CFET) stack on a substrate, the first CFET stack comprising:
a first upper transistor comprising a first upper drain region; and
a first lower transistor between the substrate and the first upper transistor, the first lower transistor comprising a first lower drain region;
a second CFET stack on the substrate, the second CFET stack comprising:
a second upper transistor comprising a second upper drain region; and
a second lower transistor between the substrate and the second upper transistor, the second lower transistor comprising a second lower drain region; and
a conductive connection that contacts the first upper drain region and the second upper drain region, wherein the conductive connection is configured to be electrically connected to a current source and is further configured to be electrically connected to a first probe of a voltage meter.