US 12,274,090 B2
Semiconductor integrated circuit device
Masahisa Iida, Yokohama (JP); and Toshihiro Nakamura, Yokohama (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on Apr. 27, 2022, as Appl. No. 17/730,881.
Application 17/730,881 is a continuation of application No. PCT/JP2019/043824, filed on Nov. 8, 2019.
Prior Publication US 2022/0254811 A1, Aug. 11, 2022
Int. Cl. H10D 84/90 (2025.01); H03K 19/177 (2020.01)
CPC H10D 84/907 (2025.01) [H03K 19/177 (2013.01); H10D 84/981 (2025.01); H10D 84/992 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device, comprising:
a core region in which an internal circuit is formed; and
an IO region located between the core region and an edge of the semiconductor integrated circuit device, the IO region including a plurality of IO cells,
wherein
one of the IO cells includes
a first output transistor of a first conductivity type connected to a first external connection pad receiving a first power supply voltage at one end and connected to an output node at the other end, and
a second output transistor of a second conductivity type connected to a second external connection pad receiving a second power supply voltage different from the first power supply voltage at one end and connected to the output node at the other end,
a capacitance transistor is provided between the first and second external connection pads,
the capacitance transistor is placed between the first and second output transistors and the edge of the semiconductor integrated circuit device as viewed in plan, and
a gate length of the capacitance transistor is smaller than gate lengths of the first and second output transistors.