US 12,274,089 B2
Stacked FET sidewall strap connections between gates
Chen Zhang, Guilderland, NY (US); Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); and Heng Wu, Guilderland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Mar. 29, 2022, as Appl. No. 17/706,675.
Prior Publication US 2023/0317727 A1, Oct. 5, 2023
Int. Cl. H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/856 (2025.01) [H01L 23/53257 (2013.01); H01L 23/535 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A set of stacked transistors, the stacked transistors comprising:
a first transistor comprising a first gate;
a second transistor comprising a second gate, wherein the second transistor is above the first transistor;
a dielectric preventing direct contact between the first gate and the second gate; and
a first sidewall strap directly connected to the first gate and to the second gate to provide an electrical path between the first gate and the second gate, wherein the first sidewall strap connects the first transistor and the second transistor.