US 12,274,087 B2
Field effect transistor and fabrication method thereof
Kuo-Chih Lai, Tainan (TW); Shih-Min Chou, Tainan (TW); Nien-Ting Ho, Tainan (TW); Wei-Ming Hsiao, Tainan (TW); Li-Han Chen, Tainan (TW); Szu-Yao Yu, Tainan (TW); and Chung-Yi Chiu, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Nov. 21, 2022, as Appl. No. 17/990,763.
Claims priority of application No. 202211272106.8 (CN), filed on Oct. 18, 2022.
Prior Publication US 2024/0128324 A1, Apr. 18, 2024
Int. Cl. H10D 62/80 (2025.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/83 (2025.01); H10D 64/27 (2025.01)
CPC H10D 62/882 (2025.01) [H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01); H10D 62/8303 (2025.01); H10D 64/513 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A field effect transistor, comprising:
a substrate having a transistor forming region thereon;
an insulating layer on the substrate;
a first graphene layer on the insulating layer within the transistor forming region;
an etch stop layer on the first graphene layer within the transistor forming region;
a first inter-layer dielectric layer on the etch stop layer;
a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region;
a second graphene layer on interior surface of the gate trench;
a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and
a gate electrode on the gate dielectric layer within the gate trench.