US 12,274,086 B2
Fabrication method for JFET with implant isolation
Clifford Drowley, Santa Clara, CA (US); Andrew P. Edwards, Santa Clara, CA (US); Subhash Srinivas Pidaparthi, Santa Clara, CA (US); and Ray Milano, Santa Clara, CA (US)
Assigned to Semiconductor Components Industries, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Mar. 8, 2024, as Appl. No. 18/600,234.
Application 18/119,717 is a division of application No. 17/131,568, filed on Dec. 22, 2020, granted, now 11,637,209, issued on Apr. 25, 2023.
Application 18/600,234 is a continuation of application No. 18/119,717, filed on Mar. 9, 2023, granted, now 11,929,440.
Claims priority of provisional application 62/953,059, filed on Dec. 23, 2019.
Prior Publication US 2024/0274725 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/83 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/85 (2025.01); H10D 84/00 (2025.01); H10D 84/83 (2025.01)
CPC H10D 30/831 (2025.01) [H10D 30/0515 (2025.01); H10D 30/62 (2025.01); H10D 62/113 (2025.01); H10D 62/8503 (2025.01); H10D 84/204 (2025.01); H10D 84/834 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A method of manufacturing a vertical junction field effect transistor (JFET), the method comprising:
providing a semiconductor substrate of a first conductivity type and having a first surface and a second surface;
forming a plurality of fins of the first conductivity type coupled to the semiconductor substrate;
forming a gate layer of a second conductivity type opposite the first conductivity type surrounding the plurality of fins;
forming an isolation region surrounding the plurality of fins; and
forming a diode region surrounding the isolation region.