| CPC H10D 30/6757 (2025.01) [H10B 10/12 (2023.02); H10B 10/18 (2023.02); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/856 (2025.01)] | 13 Claims |
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1. A semiconductor device comprising:
a plurality of first wire patterns stacked sequentially on a substrate, each of the plurality of first wire patterns extending in a first direction;
a first gate electrode surrounding the plurality of first wire patterns and extending in a second direction, the first direction intersecting the second direction perpendicularly;
a plurality of second wire patterns stacked sequentially on the substrate, each of the plurality of second wire patterns extending in the first direction;
a second gate electrode surrounding the plurality of second wire patterns and extending in the second direction;
a plurality of third wire patterns stacked sequentially on the substrate between the first and second wire patterns in the first direction, each of the plurality of third wire patterns extending in the first direction; and
a third gate electrode surrounding the plurality of third wire patterns and extending in the second direction,
wherein:
a width of each of the first wire patterns in the second direction is different from a width of each of the second wire patterns in the second direction,
each of the third wire patterns includes a first portion and a second portion adjacent to each other in the first direction, and
a width of the first portion of each of the third wire patterns in the second direction is different from a width of the second portion of each of the third wire patterns in the second direction.
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