| CPC H10B 99/00 (2023.02) | 20 Claims |

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1. A memory device, comprising:
a semiconductor substrate; and
a memory cell at a memory region of the semiconductor substrate and comprising:
a memory portion of the semiconductor substrate;
a tunneling layer over the memory portion of the semiconductor substrate;
a storage layer over and in contact with the tunneling layer;
a first electrode over and in contact with the storage layer; and
a second electrode over and in contact with the tunneling layer but spaced apart from the storage layer.
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