US 12,274,077 B2
Method of forming semiconductor memory device
Wei-Chih Wen, Hsinchu (TW); Yu-Wei Jiang, Hsinchu (TW); and Han-Jong Chia, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 26, 2022, as Appl. No. 17/825,440.
Prior Publication US 2023/0389340 A1, Nov. 30, 2023
Int. Cl. H10B 99/00 (2023.01); H01L 29/08 (2006.01); H10B 43/27 (2023.01)
CPC H10B 99/00 (2023.02) [H01L 29/0847 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor memory device comprising:
forming a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternatingly stacked in a Z direction substantially perpendicular to the substrate;
forming a plurality of source/drain trenches in the stack structure;
conformally forming a barrier layer in the source/drain trenches, and then filling the source/drain trenches with a plurality of sacrificial segments;
forming a protection layer over the stack structure to cover the barrier layer and the sacrificial segments;
removing the sacrificial layers of the stack structure to form a plurality of spaces among the dielectric layers;
forming a plurality of conductive layers in the spaces;
sequentially removing the protection layer, the sacrificial segments and the barrier layer; and
forming a plurality of memory structures in the source/drain trenches.