US 12,274,076 B2
Integrated circuit, method for manufacturing an integrated circuit, wafer and method for manufacturing a wafer
Hans Taddiken, Munich (DE); Christoph Glacer, Munich (DE); Dominik Heiss, Munich (DE); and Christoph Kadow, Gauting (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Oct. 12, 2023, as Appl. No. 18/379,423.
Application 18/379,423 is a continuation of application No. 17/192,979, filed on Mar. 5, 2021, granted, now 11,818,900.
Claims priority of application No. 20161123 (EP), filed on Mar. 5, 2020.
Prior Publication US 2024/0040803 A1, Feb. 1, 2024
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/30 (2023.02) [H10N 70/021 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02)] 10 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a transistor;
a first metallization layer above the transistor and electrically connected to the transistor; and
a phase change switch,
wherein at least a part of the phase change switch is provided below the first metallization layer,
wherein the first metallization layer is provided laterally adjacent to the phase change switch,
wherein the phase change switch comprises a heater, and
wherein the heater and a part of the transistor are each provided in a lower-level interconnect layer of the integrated circuit.