US 12,274,074 B2
Method and related apparatus for improving memory cell performance in semiconductor-on-insulator technology
Jack Liu, Taipei (TW); and Charles Chew-Yuen Young, Cupertino, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 2, 2022, as Appl. No. 17/734,315.
Application 17/094,008 is a division of application No. 16/034,647, filed on Jul. 13, 2018, granted, now 10,847,575, issued on Nov. 24, 2020.
Application 17/734,315 is a continuation of application No. 17/094,008, filed on Nov. 10, 2020, granted, now 11,329,101.
Prior Publication US 2022/0262857 A1, Aug. 18, 2022
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); G11C 13/00 (2006.01)
CPC H10B 61/22 (2023.02) [G11C 11/161 (2013.01); G11C 11/1655 (2013.01); G11C 11/1675 (2013.01); H10N 50/80 (2023.02); G11C 13/0004 (2013.01); G11C 13/0011 (2013.01); G11C 13/0069 (2013.01); G11C 2213/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor disposed on a semiconductor substrate, wherein the first transistor comprises a first source/drain region and a second source/drain region that are laterally spaced;
a second transistor disposed on the semiconductor substrate, wherein the second transistor is different than the first transistor, and wherein the second transistor comprises a first source/drain region and a second source/drain region that are laterally spaced; and
a resistive memory cell disposed over the semiconductor substrate, wherein the resistive memory cell comprises a first electrode and a second electrode, wherein the first source/drain region of the first transistor and the first source/drain region of the second transistor are electrically coupled to the first electrode, and wherein the second source/drain region of the first transistor and the second source/drain region of the second transistor are electrically coupled together;
wherein:
the first transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor; and
the second transistor is a n-channel metal-oxide-semiconductor (NMOS) transistor.