| CPC H10B 61/00 (2023.02) [H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |

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1. A method for fabricating a semiconductor memory device, the method comprising:
depositing a bottom capping layer over a substrate in a first region and a second region of the substrate;
forming a memory cell having a bottom electrode, a memory element, and a top electrode in the first region, wherein the bottom electrode is disposed in an opening of the bottom capping layer;
forming a first portion of a top capping layer on a top surface of the top electrode and extending to the second region of the substrate over the bottom capping layer;
while a masking element is disposed over the first region, performing an etching process on layers of the second region, wherein the etching process reduces a thickness of the bottom capping layer in the second region; and
after the etching process, forming a second portion of the top capping layer over the first region and the second region.
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