US 12,274,071 B1
Capacitor integrated with a transistor for logic and memory applications
Mauricio Manfrini, Heverlee (BE); Noriyuki Sato, Hillsboro, OR (US); James David Clarkson, El Sobrante, CA (US); Abel Fernandez, Berkeley, CA (US); Somilkumar J. Rathi, San Jose, CA (US); Niloy Mukherjee, San Ramon, CA (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on May 31, 2023, as Appl. No. 18/326,424.
Application 18/326,424 is a continuation of application No. 18/167,816, filed on Feb. 10, 2023, granted, now 11,765,908.
Int. Cl. H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) 22 Claims
OG exemplary drawing
 
1. A device comprising:
a transistor above a substrate;
an electrode structure coupled with a terminal of the transistor;
a plate electrode coupled with the electrode structure, the plate electrode comprising at least a first conductive layer and a second conductive layer on the first conductive layer and wherein the first conductive layer is part of a first die, and the second conductive layer is part of a second die; and
a planar capacitor comprising a non-linear polar dielectric material having a form ABOX, wherein A and B are two different cations, and wherein X is 1, 2, or 3.