US 12,274,070 B2
Semiconductor device and manufacturing method thereof
Po-Ting Lin, Taichung (TW); Wei-Chih Wen, Hsinchu County (TW); Kai-Wen Cheng, Taichung (TW); Wu-Wei Tsai, Taoyuan (TW); Yu-Ming Hsiang, New Taipei (TW); Yan-Yi Chen, Taipei (TW); Hai-Ching Chen, Hsinchu (TW); Yu-Ming Lin, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 4, 2022, as Appl. No. 17/857,047.
Prior Publication US 2024/0008287 A1, Jan. 4, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H10B 53/20 (2023.01)
CPC H10B 53/20 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09)] 17 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate having a dielectric layer thereon with a metallic via therein;
a transistor structure disposed on the metallic via and the dielectric layer, wherein the transistor structure includes:
a gate layer disposed on and in contact with the metallic via;
a gate dielectric layer and a semiconductor channel layer disposed on the gate layer; and
source and drain terminals on the semiconductor channel layer; and
a ferroelectric capacitor structure electrically connected with the transistor structure, wherein the ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between, and the ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer, and materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.