| CPC H10B 43/40 (2023.02) [H10B 41/20 (2023.02); H10B 41/42 (2023.02); H10B 43/20 (2023.02)] | 20 Claims |

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1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a transistor in a first region on a first side of a single crystalline silicon substrate;
forming a step layer in a second region on the first side of the single crystalline silicon substrate;
forming a channel structure extending through a stack structure and in contact with the step layer without extending through the step layer, the stack structure comprising interleaved dielectric layers and conductive layers on the step layer; and
removing part of the single crystalline silicon substrate that is in the second region from a second side opposite to the first side of the single crystalline silicon substrate to expose the step layer from the second side and retaining another part of the single crystalline silicon substrate, corresponding to the transistor, in the first region.
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