US 12,274,066 B2
Memory peripheral circuit having three-dimensional transistors and method for forming the same
Chao Sun, Wuhan (CN); Liang Chen, Wuhan (CN); Wu Tian, Wuhan (CN); Wenshan Xu, Wuhan (CN); Wei Liu, Wuhan (CN); Ning Jiang, Wuhan (CN); and Lei Xue, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 22, 2021, as Appl. No. 17/482,026.
Application 17/482,026 is a continuation of application No. PCT/CN2021/103723, filed on Jun. 30, 2021.
Claims priority of application No. PCT/CN2021/093323 (WO), filed on May 12, 2021.
Prior Publication US 2022/0367504 A1, Nov. 17, 2022
Int. Cl. H10B 43/40 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/41 (2023.01)
CPC H10B 43/40 (2023.02) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/41 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of memory cells;
a plurality of bit lines coupled to the array of memory cells; and
a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells,
wherein;
a first peripheral circuit of the plurality of peripheral circuits comprises a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines, and a second peripheral circuit of the plurality of peripheral circuits comprises a second 3D transistor coupled to the array of memory cells through at least one of a plurality of word lines;
the first 3D transistor comprises a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; and
a first voltage provided to the first 3D transistor is lower than a second voltage provided to the second 3D transistor, the second voltage provided to the second 3D transistor of the second peripheral circuit being configured to select one word line of the plurality of word lines to apply a third voltage on the word line, and the gate structure of the first 3D transistor comprising edges arranged over sidewalls of the 3D semiconductor body.