US 12,274,057 B2
Methods of forming integrated circuit structures comprising isolation structures with different depths
Michael A. Smith, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Dec. 8, 2023, as Appl. No. 18/533,291.
Application 18/533,291 is a division of application No. 17/508,353, filed on Oct. 22, 2021, granted, now 11,889,687.
Application 17/508,353 is a continuation of application No. 16/527,552, filed on Jul. 31, 2019, granted, now 11,171,148, issued on Nov. 9, 2021.
Prior Publication US 2024/0107754 A1, Mar. 28, 2024
Int. Cl. H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming an isolation structure, comprising:
forming a first conductive region in a first section of a semiconductor material;
forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material that is opposite the first side of the first section of the semiconductor material;
extending the first trench to a depth below the first conductive region, extending the second trench to the depth below the first conductive region, and removing a portion of the first section of the semiconductor material overlying the first conductive region;
forming a second conductive region in the semiconductor material below a bottom of the first trench and forming a third conductive region in the semiconductor material below a bottom of the second trench; and
forming a dielectric material overlying the first conductive region and filling the first trench and the second trench.