US 12,274,051 B2
Metal gate memory device and method
Hyucksoo Yang, Meridian, ID (US); Jongpyo Kim, Boise, ID (US); and Byung Yoon Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 11, 2022, as Appl. No. 17/717,406.
Prior Publication US 2023/0328966 A1, Oct. 12, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 11/4091 (2006.01); G11C 11/4097 (2006.01); H01B 1/02 (2006.01); H01L 29/51 (2006.01); H10B 12/00 (2023.01); H01Q 1/22 (2006.01)
CPC H10B 12/48 (2023.02) [G11C 11/4091 (2013.01); G11C 11/4097 (2013.01); H01B 1/02 (2013.01); H01L 29/517 (2013.01); H10B 12/05 (2023.02); H01Q 1/2258 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of memory cells;
a transistor located on a periphery of the array of memory cells, the transistor including a channel region with a first metal gate formed over the channel region and separated from the channel region by a gate oxide; and
a number of data lines coupled to memory cells in the array, wherein the number of data lines physically extend over the first metal gate, the number of data lines formed from a second metal, and wherein a bottom side of the number of data lines forms a direct interface with the first metal gate, without any intervening structure between the bottom side of the number of data lines and the first metal gate.