US 12,274,046 B2
Cross FET SRAM cell layout
Richard T. Schultz, Ft. Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Oct. 3, 2023, as Appl. No. 18/480,463.
Application 18/480,463 is a continuation of application No. 17/489,252, filed on Sep. 29, 2021, granted, now 11,778,803, issued on Oct. 3, 2023.
Prior Publication US 2024/0032270 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 10/00 (2023.01); G11C 7/10 (2006.01); H01L 29/423 (2006.01)
CPC H10B 10/12 (2023.02) [G11C 7/1045 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an array of memory bit cells for storing data arranged as a plurality of rows and a plurality of columns, wherein a given memory bit cell of the array comprises a single via between two drain regions of two transistors that include channels of opposite doping polarities; and
wherein in response to receiving an indication of a read operation targeting a row of the plurality of rows comprising the given memory bit cell, the array is configured to convey data stored in the given memory bit cell to a read bit line.