US 12,274,045 B2
Well pick-up region design for improving memory macro performance
Chih-Chuan Yang, Hsinchu (TW); Chang-Ta Yang, Hsinchu (TW); and Ping-Wei Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Feb. 19, 2024, as Appl. No. 18/444,889.
Application 17/873,626 is a division of application No. 16/657,421, filed on Oct. 18, 2019, granted, now 11,600,623, issued on Mar. 7, 2023.
Application 18/444,889 is a continuation of application No. 17/873,626, filed on Jul. 26, 2022, granted, now 11,910,585.
Claims priority of provisional application 62/771,455, filed on Nov. 26, 2018.
Prior Publication US 2024/0237323 A1, Jul. 11, 2024
Int. Cl. H10B 10/00 (2023.01); G06F 30/30 (2020.01); G11C 11/412 (2006.01)
CPC H10B 10/00 (2023.02) [G06F 30/30 (2020.01); G11C 11/412 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a circuit region;
a first well pick-up (WPU) region;
a second WPU region, wherein the circuit region, the first WPU region, and the second WPU region are arranged along a first direction in sequence;
a first well of a first conductivity type, wherein the first well has a first portion disposed in the circuit region and a second portion disposed in the first WPU region; and
a second well of a second conductivity type different from the first conductivity type, wherein the second well has a first portion disposed in the circuit region, a second portion disposed in the first WPU region, and a third potion disposed in the second WPU region,
wherein measured along the first direction a width of the first WPU region is less than a width of the second WPU region.