| CPC H04W 72/569 (2023.01) [H04W 72/1268 (2013.01); H04W 72/23 (2023.01)] | 20 Claims |

|
1. An apparatus comprising:
a processor;
memory coupled with the processor, and
instructions stored in the memory and executable by the processor to cause the apparatus to:
receive a downlink channel transmission carrying a downlink control information format that schedules a first uplink channel transmission;
determine an overlap between the first uplink channel transmission and a second uplink channel transmission, wherein the first uplink channel transmission is associated with a first priority, wherein the second uplink channel transmission is associated with a second priority different than the first priority; and
cancel the second uplink channel transmission before a symbol associated with the overlap between the first uplink channel transmission and the second uplink channel transmission,
wherein the symbol associated with the overlap is based on timing related to receiving the downlink channel transmission carrying the downlink control information format.
|