| CPC H04W 72/02 (2013.01) [H04W 72/0446 (2013.01); H04W 72/20 (2023.01); H04W 76/20 (2018.02); H04W 92/18 (2013.01)] | 27 Claims |

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1. An apparatus comprising:
wherein the processor circuit is arranged for a sidelink communication,
wherein the sidelink communication comprises at least one sidelink frames,
wherein each of the at least one sidelink frames have a control region and a data region,
wherein the control region comprises a first control region and a second control region,
wherein the first control region comprises basic information regarding a sidelink transmission of a packet,
wherein the second control region comprises information regarding data transmission resource location or data transmission resource locations of the packet,
wherein the processor circuit is arranged to transmit the packet using more than a single data transmission resource location in a single sidelink frame such that the packet or multiple redundant, versions of the packet is/are to transmitted in data transmission resource locations across the at least one sidelink frames and at least one subsequent sidelink frames.
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