| CPC H04N 25/78 (2023.01) [G06F 1/08 (2013.01); H01L 25/0753 (2013.01); H01L 25/18 (2013.01); H03K 19/018521 (2013.01); H03L 7/099 (2013.01); H04N 25/60 (2023.01); H04N 25/627 (2023.01); H04N 25/63 (2023.01); H04N 25/709 (2023.01); H04N 25/77 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/7795 (2023.01); H10F 39/026 (2025.01); H10F 39/8037 (2025.01); H10F 39/811 (2025.01)] | 18 Claims |

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1. An image sensor, comprising:
a first pixel circuit, comprising:
a first pixel unit;
a first transfer transistor, coupled to the first pixel unit and a first floating diffusion node;
a first readout transistor, coupled to the first floating diffusion node;
a first ramp capacitor, coupled to the first floating diffusion node, and receiving a first ramp signal; and
a first reset transistor, coupled to the first floating diffusion node, and receiving a reset signal;
a ramp signal generator, coupled to the first ramp capacitor, and configured to provide the first ramp signal; and
a ramp signal controller, coupled to the ramp signal generator,
wherein the image sensor is a digital correlated double sampling circuit, the first ramp signal additionally generates an offset voltage through the ramp signal controller, so that a voltage range or a counting result of the pixel circuit during at least one of a reset period and a readout period has an offset,
wherein the ramp signal generator provides the offset voltage during at least one of the readout period and the reset period according to a digital number.
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