US 12,273,641 B2
Solid-state imaging element and imaging device
Daisuke Nakagawa, Kanagawa (JP); Takashi Moue, Kanagawa (JP); and Yoshio Awatani, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/040,859
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jun. 25, 2021, PCT No. PCT/JP2021/024083
§ 371(c)(1), (2) Date Feb. 7, 2023,
PCT Pub. No. WO2022/038895, PCT Pub. Date Feb. 24, 2022.
Claims priority of application No. 2020-138540 (JP), filed on Aug. 19, 2020; and application No. 2021-073876 (JP), filed on Apr. 26, 2021.
Prior Publication US 2023/0300485 A1, Sep. 21, 2023
Int. Cl. H04N 25/709 (2023.01); H01L 27/146 (2006.01)
CPC H04N 25/709 (2023.01) [H01L 27/14634 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A solid-state imaging element comprising:
an input transistor configured to output, from a drain, a potential within a range from one side to the other side of a pair of output potentials on a basis of whether or not an input potential input to a source and a predetermined reference potential input to a gate substantially coincide with each other;
a first current source configured to supply a constant current;
a capacitor that is inserted between the source of the input transistor and the first current source; and
a first cutoff switch configured to disconnect the drain of the input transistor from a connection node within a predetermined period for initializing the connection node between the capacitor and the first current source to a lower one of the pair of output potentials, and connect the connection node with the drain of the input transistor outside the predetermined period.