US 12,273,282 B2
System-in-package network processors
Kevin Clark, San Jose, CA (US); Scott J. Weber, Piedmont, CA (US); Ravi Prakash Gutala, San Jose, CA (US); and Aravind Raghavendra Dasu, Milpitas, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 26, 2024, as Appl. No. 18/587,744.
Application 18/587,744 is a continuation of application No. 18/177,417, filed on Mar. 2, 2023, granted, now 11,916,811.
Application 18/177,417 is a continuation of application No. 17/528,005, filed on Nov. 16, 2021, granted, now 11,611,518, issued on Mar. 21, 2023.
Application 17/528,005 is a continuation of application No. 16/369,889, filed on Mar. 29, 2019, granted, now 11,190,460, issued on Nov. 30, 2021.
Prior Publication US 2024/0205167 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 49/109 (2022.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H04L 49/15 (2022.01)
CPC H04L 49/109 (2013.01) [H01L 25/0652 (2013.01); H04L 49/15 (2013.01); H01L 23/5386 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a base die that comprises memory; and
an application-specific integrated circuit die coupled to the base die via an interface, wherein the application-specific integrated circuit die and the base die are vertically aligned so the base die is vertically below at least a portion of a surface area of the application-specific integrated circuit die with a region of the application-specific integrated circuit die being vertically aligned with a corresponding region-aligned memory of the memory of the base die that is allocated to the region, wherein the application-specific integrated circuit die is to implement a processing function that uses the region-aligned memory.