| CPC H04L 45/74 (2013.01) [H04L 45/42 (2013.01)] | 20 Claims |
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1. A circuit, comprising:
a memory array having a plurality of memory devices arranged in a plurality of rows and columns and a plurality of passthrough channels connecting non-adjacent memory devices, each of the memory devices including:
a memory configured to store packet data, and
a packet router configured to interface with at least one non-adjacent memory device of the memory array, the packet router configured to: 1) determine a destination address for a packet, and 2) based on the destination address, selectively forward the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels, the passthrough channel being routed through an adjacent memory device located between the memory device and the non-adjacent memory device, the passthrough channel being communicatively decoupled from a memory and a packet router of the adjacent memory device; and
a memory interface configured to route the packet from a source to the memory array, the memory interface selectively forwarding the packet to one of the plurality of memory devices based on the destination address;
wherein the memory interface is further configured to append the destination address to the packet prior to forwarding the packet to the memory array, the appending including a target identifier (ID) indicating XY coordinates within the memory array for the one of the plurality of memory devices.
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